1. Field of the Invention
The present invention relates to techniques for prioritizing interrupt requests generated by a plurality of interrupt sources.
2. Description of the Prior Art
When devices within a data processing system require a processor within the data processing system, typically the CPU, to perform a service routine, they will typically issue an interrupt request to that processor. When an interrupt request is received by the processor whilst it is executing a main process, the processor will typically temporarily interrupt the main process under execution, and instead execute the Interrupt Service Routine (ISR) specified by the interrupt request. The devices may be on the same chip as the processor, or may be off-chip. In a typical data processing system there will often be multiple devices which can issue such interrupt requests, and since the processor cannot simultaneously execute the ISRs defined by the plurality of interrupt requests, it is known to provide an interrupt controller for receiving the various interrupt requests, and prioritizing between them. Hence, interrupt requests from certain devices (for example a network interface) can be given higher priority than interrupt requests from other devices (for example a keyboard).
In a vectored interrupt controller (VIC) the controller will store a list of vector addresses for ISRs that are associated with each interrupt source, i.e. each device that can issue an interrupt request. Hence, when an interrupt request is received, the VIC can pass the exact location of the associated ISR code to the processor to enable the processor to begin execution of that ISR.
As data processing systems become more complex, then typically the number of interrupt sources increases. To handle this increase in interrupt sources, larger VICs can be designed having more inputs for receiving the interrupt requests from the various interrupt sources, but this results in the VIC incorporating more logic gates, and accordingly consuming more power. Further, the VIC will be larger in die area, thus giving rise to larger production costs. Accordingly, to keep the power consumption and production costs acceptable, a VIC is typically designed to have a number of inputs sufficient for many normal implementations, but not necessarily sufficient for all implementations, and hence for example VICs having 8, 16 or 32 interrupt source inputs are known.
However, there are an increasing number of systems where the number of interrupt sources exceeds that that can be handled by a single VIC, for example there is a tendency for the number of interrupt sources available in a System on Chip (SoC) to increase beyond that that can be handled by a single VIC. To facilitate the increasing number of interrupt sources available in such systems, it is known to develop a daisy chain consisting of a number of interrupt controllers, such as illustrated schematically in FIG. 1. In the example illustrated in FIG. 1, seven VICs 100, 110, 120, 130, 140, 150 and 160 are daisy chained together, with the VIC 100 being responsible for outputting the interrupt request to the CPU. Each interrupt request 170 issued to the CPU is accompanied by a corresponding vector address 180 specifying the location of the ISR to be executed by the CPU to process the interrupt request.
It is usual in such daisy chain techniques for the VICs higher in the daisy chain (i.e. closer to the CPU) to block higher level (i.e. higher priority) interrupt requests than the interrupt request currently being serviced in situations where that higher level interrupt request is generated by VICs lower in the chain (i.e. further from the CPU). One standard approach is illustrated in FIG. 2A, where a fixed priority level is set for interrupt requests received from a VIC lower in the chain (such interrupt requests being referred to herein as daisy chain interrupt requests). In the FIG. 2A example, CPU 200 is arranged to receive interrupt requests from the VIC 240. The VIC 240 is arranged to receive interrupt requests directly from certain interrupt sources, for example the interrupt request IRQ0 received over path 212 from interrupt source 0, and is further arranged to receive a daisy chain interrupt request 222, along with the corresponding daisy chain vector address 224, from the VIC 220.
In the example illustrated in FIG. 2A, any daisy chain interrupt request 222 from the VIC 220 will be assigned a fixed priority level, in this example the level hexadecimal F (which might typically be the lowest priority level). This is required since the priority encoding logic within the VIC 240 requires each input interrupt source to have a corresponding priority level associated with it to enable the priority encoding logic to be able to arbitrate between multiple interrupt requests received at the same time.
As a result, if the IRO0 interrupts request is received over path 212 at a time when no other interrupts are being processed, this will result in that interrupt request being output from the VIC 240 to the CPU 200 over path 202, along with the corresponding vector address determined by the VIC 240 being output over path 204 to the CPU 200. If whilst that interrupt request is being processed by the CPU 200, the interrupt request IRQ9 is received over path 214 at the VIC 220, this will result in a corresponding daisy chain interrupt request being out put over path 222, along with the corresponding vector address over path 224. In the example illustrated in FIG. 2A, priority levels having low numerical values indicate higher priorities, and accordingly the IRQ9 interrupt request has the highest priority level, i.e. level 0. However, the VIC 210 will treat the corresponding daisy chain interrupt request as having the priority level hexadecimal F, and accordingly will suppress generation of a corresponding interrupt request on path 202 whilst the IRQ0 interrupt request is being processed.
FIG. 2B illustrates an alternative prior art approach, where instead of a fixed priority level hard-coded into the VIC 240, the interrupt controller 240 has a separate priority register 242 identifying the priority for any daisy chain interrupt request received over path 222 from VIC 220. The value in this priority register 242 is programmable, but again is typically set at a relatively low priority level. It will be appreciated that the daisy chained VIC system illustrated in FIG. 2B operates in an analogous manner to that system shown in FIG. 2A, the only difference being that the priority level set within the priority register 242 is used rather than the fixed priority level of the FIG. 2A system. Accordingly, it will be seen that whenever the priority value stored in the priority register 242 represents a lower priority than level 5, then again whilst the IRQ0 interrupt is being processed by the CPU 200, no other interrupt request received by the VIC 220 will be processed, even if they have a higher priority than level 5.
As another example, if the interrupt request IRQ7 is received by VIC 220 over path 216 at a time when no other interrupts are being requested, the corresponding daisy chain interrupt request received over path 222, along with its corresponding vector address over path 224, will be routed on by the VIC 240 over paths 202, 204 to the CPU 200. However, in doing so, the priority level for IRQ7 will be reset within VIC 240 to the level stored within the priority register 242, which may by way of illustration be priority level 5. If whilst IRQ7 is being serviced by the CPU, IRQ9 having a level 0 priority (i.e. the highest priority) is asserted, VIC 220 passes the IRQ9 request through to VIC 240 as a corresponding daisy chain interrupt request. However, assuming the value in the priority register 242 is not changed, VIC 240 will then treat this daisy chain interrupt request as having a priority level 5, and will block it from reaching the CPU 200 until the CPU 200 has finished processing the IRQ7 interrupt request.
Hence, the register 242 effectively resets the priority of an interrupt request generated by a VIC lower in the daisy chain, in this example VIC 220, to the value programmed in that register. The user could change the value in the register 242 during the lower level interrupt to allow higher level interrupts to be serviced, but it will be appreciated that this adds overhead to the interrupt service routine. Hence, it can be seen with both of these prior art techniques that VICs higher in the daisy chain will block higher level interrupts than the one currently being serviced when those higher level interrupts are generated by a VIC lower in the daisy chain.
It is an object of the present invention to provide a technique which alleviates such blocking problems.